Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials, for example, strontium bismuth tantalum (SBT) can also be used. FIG. 1 shows a conventional ferroelectric memory cell 100 having a transistor 130 and a ferroelectric capacitor 140. An electrode 142 is coupled to a plateline 170 and another electrode 141 is coupled to the transistor which selectively couples or decouples the capacitor from a bitline 160, depending on the state (active or inactive) of a wordline 150 coupled to the transistor gate.
The ferroelectric memory stores information in the capacitor as remanent polarization. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed; resulting in a non-volatile memory cell.
FIG. 2 shows a cross section of a conventional ferroelectric capacitor 140 on a plug 266. As shown, the capacitor comprises a ferroelectric layer 246 sandwiched between first and second electrodes 141 and 142. The electrodes typically are formed from a noble metal such as platinum. The lower electrode 141 is coupled to the plug which, for example, is in contact with a diffusion region of the cell transistor. A barrier layer 264 can be provided below the lower electrode to protect the plug from oxidation. An encapsulation layer 283 surrounds the top and side of the capacitor, protecting the capacitor from diffusion of, for example, oxygen.
A contact opening 260 is formed in a dielectric layer 280, exposing the upper electrode. A contact is formed in the opening to couple the upper electrode to, for example, a plateline. The contact opening is formed by an anisotropic etch such as reactive ion etch (RIE). Etch damage to the upper electrode occurs during the formation of the contact opening. To repair the damage, a recovery anneal is necessary. However, the high temperature of the recovery anneal, typically about 500-700xc2x0 C., oxidizes the plug. Oxidation increases contact resistance, thereby degrading the plug. Such degradation adversely impacts the reliability of the IC and reduces yields.
From the foregoing discussion, it is desirable to provide a ferroelectric memory IC with improved reliability and yields.
The invention relates to memory cells employed in ICs, such as memory ICs or other types of ICs. More particularly, the invention relates to improving the reliability of capacitors. In one embodiment a capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact for coupling to the top electrode is provided. In one embodiment of the invention, at least a portion of the contact is offset from the capacitor. In one embodiment, the capacitor is a ferroelectric capacitor. Other types of capacitors are also useful. By offsetting the contract contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.